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1 features ? utilizes the arm7tdmi ? arm thumb processor core ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? leader in mips/watt ? embedded ice (in-circuit emulation) 8k bytes internal sram fully-programmable external bus interface (ebi) ? maximum external address space of 128m bytes ?8chipselects ? software programmable 8/16-bit external databus 8-level priority, individually maskable, vectored interrupt controller ? 7 external interrupts, including a high-priority, low-latency interrupt request 58 programmable i/o lines 6-channel 16-bit timer/counter ? 6 external clock inputs and 2 multi-purpose i/o pins per channel 3usarts master/slave spi interface ? 8-bit to 16-bit programmable data length ? 4 external slave chip selects programmable watchdog timer 8-channel 10-bit adc 2-channel 10-bit dac clock generator with on-chip main oscillator and pll for multiplication ? 3 to 20 mhz frequency range main oscillator real-time clock with on-chip 32 khz oscillator ? battery backup operation and external alarm 8-channel peripheral data controller for usarts and spis advanced power management controller (apmc) ? normal, wait, slow, standby and power-down modes ieee 1149.1 jtag boundary-scan on all digital pins fully static operation: 0 hz to 33 mhz internal frequency range at vddcore = 3.0v, 85 c 2.7v to 3.6v core operating range, 2.7v to 5.5v i/o operating range 2.7v to 3.6v analog operating range 1.8v to 3.6v backup battery operating range 2.7v to 3.6v oscillator and pll operating range -40 cto+85 c temperature range available in a 176-lead tqfp or 176-ball bga package description the AT91M55800A is a member of the atmel at91 16/32-bit microcontroller family, which is based on the arm7tdmi processor core. this processor has a high-perfor- mance 32-bit risc architecture with a high-density 16-bit instruction set and very low power consumption. in addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. the fully programmable external bus interface provides a direct connection to off-chip memory in as fast as one clock cycle for a read or write operation. an eight-level prior- ity vectored interrupt controller in conjunction with the peripheral data controller significantly improve the real-time performance of the device. the device is manufactured using atmel?s high-density cmos technology. by combin- ing the arm7tdmi processor core with an on-chip sram, a wide range of peripheral functions, analog interfaces and low-power oscillators on a monolithic chip, the atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and cost- effective solution to many ultra low-power applications. at91 arm ? thumb ? microcontrollers AT91M55800A summary rev. 1745cs?atarm?05/02 note: this is a summary document. a complete document is available on our web site at www.atmel.com.
2 AT91M55800A 1745cs?atarm?05/02 pin configurations notes: 1. analog pins 2. battery backup pins table 1 . pin configuration for 176-lead tqfp package pin AT91M55800A pin AT91M55800A pin AT91M55800A pin AT91M55800A 1 gnd 45 gnd 89 gnd 133 gnd 2 gnd 46 gnd 90 gnd 134 gnd 3 ncs0 47 d8 91 pa19/rxd1 135 ncs4 4 ncs1 48 d9 92 pa20/sck2 136 ncs5 5 ncs2 49 d10 93 pa21/txd2 137 ncs6 6 ncs3 50 d11 94 pa22/rxd2 138 ncs7 7 nlb/a0 51 d12 95 pa23/spck 139 pb0 8 a1 52 d13 96 pa24/miso 140 pb1 9 a2 53 d14 97 pa25/mosi 141 pb2 10 a3 54 d15 98 pa26/npcs0/nss 142 pb3/irq4 11 a4 55 pb19/tclk0 99 pa27/npcs1 143 pb4/irq5 12 a5 56 pb20/tioa0 100 pa28/npcs2 144 pb5 13 a6 57 pb21/tiob0 101 pa29/npcs3 145 pb6/ad0trig 14 a7 58 pb22/tclk1 102 vddio 146 pb7/ad1trig 15 vddio 59 vddio 103 gnd 147 vddio 16 gnd 60 gnd 104 vddpll 148 gnd 17 a8 61 pb23/tioa1 105 xin 149 pb8 18 a9 62 pb24/tiob1 106 xout 150 pb9 19 a10 63 pb25/tclk2 107 gndpll 151 pb10 20 a11 64 pb26/tioa2 108 pllrc 152 pb11 21 a12 65 pb27/tiob2 109 vddbu (2) 153 pb12 22 a13 66 pa0/tclk3 110 xin32 (2) 154 pb13 23 a14 67 pa1/tioa3 111 xout32 (2) 155 pb14 24 a15 68 pa2/tiob3 112 nrstbu (2) 156 pb15 25 a16 69 pa3/tclk4 113 gndbu (2) 157 pb16 26 a17 70 pa4/tioa4 114 wakeup (2) 158 pb17 27 a18 71 pa5/tiob4 115 shdn (2) 159 nwdovf 28 a19 72 pa6/tclk5 116 gndbu (2) 160 mcko 29 vddio 73 vddio 117 vdda (1) 161 vddio 30 gnd 74 gnd 118 ad0 (1) 162 gnd 31 a20 75 pa7/tioa5 119 ad1 (1) 163 pb18/bms 32 a21 76 pa8/tiob5 120 ad2 (1) 164 jtagsel 33 a22 77 pa9/irq0 121 ad3 (1) 165 tms 34 a23 78 pa10/irq1 122 ad4 (1) 166 tdi 35 d0 79 pa11/irq2 123 ad5 (1) 167 tdo 36 d1 80 pa12/irq3 124 ad6 (1) 168 tck 37 d2 81 pa13/fiq 125 ad7 (1) 169 ntrst 38 d3 82 pa14/sck0 126 advref (1) 170 nrst 39 d4 83 pa15/txd0 127 davref (1) 171 nwait 40 d5 84 pa16/rxd0 128 da0 (1) 172 noe/nrd 41 d6 85 pa17/sck1 129 da1 (1) 173 nwe/nwr0 42 d7 86 pa18/txd1/ntri 130 gnda (1) 174 nub/nwr1 43 vddcore 87 vddcore 131 vddcore 175 vddcore 44 vddio 88 vddio 132 vddio 176 vddio
3 AT91M55800A 1745cs?atarm?05/02 table 2 . pin configuration for 176-ball bga package pin AT91M55800A pin AT91M55800A pin AT91M55800A pin AT91M55800A a1 ncs1 c1 a0/nlb e1 a4 g1 a12 a2 nwait c2 ncs0 e2 a3 g2 a9 a3 nrst c3 vddio e3 a5 g3 a8 a4 ntrst c4 vddcore e4 gnd g4 gnd a5 pb18/bms c5 tms e5 ? g5 ? a6 nwdovf c6 vddio e6 ? g6 ? a7 pb16 c7 mck0 e7 ? g7 ? a8 pb12 c8 pb13 e8 ? g8 ? a9 pb10 c9 pb6/ad0trig e9 ? g9 ? a10 pb9 c10 vddio e10 ? g10 ? a11 pb8 c11 pb4/irq5 e11 ? g11 ? a12 ncs7 c12 pb0 e12 ad6 g12 ad3 a13 ncs6 c13 vddio e13 ad5 g13 ad2 a14 gnd c14 da0 e14 nrstbu g14 gnd a15 davref c15 advref e15 gndbu g15 xin32 b1 ncs2 d1 a2 f1 a10 h1 a15 b2 nub/nwr1 d2 a1 f2 a7 h2 a14 b3 nwe/nwr0 d3 ncs3 f3 vddio h3 a13 b4 noe/nrd d4 gnd f4 a6 h4 a11 b5 td0 d5 tck f5 ? h5 ? b6 tdi d6 jtagsel f6 ? h6 ? b7 pb17 d7 gnd f7 ? h7 ? b8 pb11 d8 pb15 f8 ? h8 ? b9 pb7/ad1trig d9 pb14 f9 ? h9 ? b10 pb3/irq4 d10 pb5 f10 ? h10 ? b11 pb2 d11 pb1 f11 ? h11 ? b12 ncs5 d12 gnd f12 gnd h12 ad1 b13 ncs4 d13 vddcore f13 ad4 h13 ad0 b14 da1 d14 ad7 f14 vddbu h14 wakeup b15 gnda d15 vdda f15 xout32 h15 gnd
4 AT91M55800A 1745cs?atarm?05/02 j1 a17 l1 a20 n1 d4 r1 d10 j2 a18 l2 a23 n2 d6 r2 d11 j3 vddio l3 d0 n3 vddio r3 d12 j4 a16 l4 d1 n4 d14 r4 d13 j5 ? l5 ? n5 pb19/tclk0 r5 pb20/tioa0 j6 ? l6 ? n6 vddio r6 pb23/tioa1 j7 ? l7 ? n7 pb25/tclk2 r7 pb24/tiob1 j8 ? l8 ? n8 pa1/tioa3 r8 pa3/tclk4 j9 ? l9 ? n9 vddio r9 pa4/tioa4 j10 ? l10 ? n10 pa8/tiob5 r10 pa5/tiob4 j11 ? l11 ? n11 pa9/irq0 r11 pa6/tclk5 j12 pa29/npcs3 l12 pa25/mosi n12 vddcore r12 pa12/irq3 j13 shdn l13 pa22rxd2 n13 vddio r13 pa14/sck0 j14 vddpll l14 pa26/npcs0/nss n14 pa19/rxd1 r14 pa15/txd0 j15 pllrc l15 xout n15 gnd r15 pa16/rxd0 k1 a19 m1 d2 p1 d5 k2 a22 m2 d3 p2 d7 k3 a21 m3 vddcore p3 d8 k4 gnd m4 gnd p4 d9 k5 ? m5 gnd p5 d15 k6 ? m6 pb21/tiob0 p6 pb22/tclk1 k7 ? m7 gnd p7 pb26/tioa2 k8 ? m8 pb27/tiob2 p8 pa2/tiob3 k9 ? m9 pa0/tclk3 p9 pa7/tioa5 k10 ? m10 gnd p10 pa10/irq1 k11 ? m11 pa23/spck p11 pa11/irq2 k12 pa28/npcs2 m12 gnd p12 pa13/fiq k13 vddio m13 pa21/txd2 p13 pa17sck1 k14 pa27/npcs1 m14 pa24/miso p14 pa18/txd1/ntri k15 gndpll m15 xin p15 pa20/sck2 table 2 . pin configuration for 176-ball bga package (continued) pin AT91M55800A pin AT91M55800A pin AT91M55800A pin AT91M55800A
5 AT91M55800A 1745cs?atarm?05/02 figure 1. 176-lead tqfp pinout figure 2. 176-ball bga pinout 144 176 133 132 89 45 88 123456789101112 a b c d e f g h j k l m n p r 13 14 15
6 AT91M55800A 1745cs?atarm?05/02 pin description table 3 . pin description module name function type active level comments ebi a0 - a23 address bus output ? d0 - d15 data bus i/o ? ncs0 - ncs7 chip select output low nwr0 lower byte 0 write signal output low used in byte-write option nwr1 lower byte 1 write signal output low used in byte-write option nrd read signal output low used in byte-write option nwe write enable output low used in byte-select option noe output enable output low used in byte-select option nub upper byte-select output low used in byte-select option nlb lower byte-select output low used in byte-select option nwait wait input input low bms boot mode select input ? sampled during reset aic irq0 - irq5 external interrupt request input ? pio-controlled after reset fiq fast external interrupt request input ? pio-controlled after reset timer tclk0 - tclk5 timer external clock input ? pio-controlled after reset tioa0 - tioa5 multipurpose timer i/o pin a i/o ? pio-controlled after reset tiob0 - tiob5 multipurpose timer i/o pin b i/o ? pio-controlled after reset usart sck0 - sck2 external serial clock i/o ? pio-controlled after reset txd0 - txd2 transmit data output output ? pio-controlled after reset rxd0 - rxd2 receive data input input ? pio-controlled after reset spi spck spi clock i/o ? pio-controlled after reset miso master in slave out i/o ? pio-controlled after reset mosi master out slave in i/o ? pio-controlled after reset nss slave select input low pio-controlled after reset npcs0 - npcs3 peripheral chip select output low pio-controlled after reset pio pa0 - pa29 parallel i/o port a i/o ? input after reset pb0 - pb27 parallel i/o port b i/o ? input after reset wd nwdovf watchdog timer overflow output low open drain adc ad0 - ad7 analog input channels 0 - 7 analog in ? ad0trig adc0 external trigger input ? pio-controlled after reset ad1trig adc1 external trigger input ? pio-controlled after reset advref analog reference analog ref ? dac da0 - da1 analog output channels 0 - 1 analog out ? davref analog reference analog ref ?
7 AT91M55800A 1745cs?atarm?05/02 clock xin main oscillator input input ? xout main oscillator output output ? pllrc rc filter for pll input ? xin32 32 khz oscillator input input ? xout32 32 khz oscillator output output ? mcko system clock output ? apmc wakeup wakeup request input ? shdn shutdown request output ? tri-state after backup reset reset nrst hardware reset input input low schmidt trigger nrstbu hardware reset input for battery part input low schmidt trigger ntri tri-state mode select input low sampled during reset jtag/ice jtagsel selects between ice and jtag mode input ? tms test mode select input ? schmidt trigger, internal pull-up tdi test data input input ? schmidt trigger, internal pull-up tdo test data output output ? tck test clock input ? schmidt trigger, internal pull-up ntrst test reset input input low schmidt trigger, internal pull-up power vdda analog power analog pwr ? gnda analog ground analog gnd ? vddbu power backup power ? gndbu ground backup ground ? vddcore digital core power power ? vddio digital i/o power power ? vddpll main oscillator and pll power power ? gnd digital ground ground ? gndpll pll ground ground ? table 3 . pin description (continued) module name function type active level comments
8 AT91M55800A 1745cs?atarm?05/02 block diagram figure 3. AT91M55800A arm7tdmi core embedded ice reset ebi: external bus interface internal ram 8k bytes asb controller aic: advanced interrupt controller amba bridge tc: timer counter block 0 tc0 tc1 tc2 usart0 usart1 2 pdc channels 2 pdc channels apb asb p i o b p i o a p i o b nrst d0 - d15 a1 - a23 a0/nlb nrd/noe nwr0/nwe nwr1/nub ncs0 - ncs7 pb19/tclk0 pb22/tclk1 pb25/tclk2 pb20/tioa0 pb21/tiob0 pb23/tioa1 pb24/tiob1 pb26/tioa2 pb27/tiob2 pa10/irq1 pa11/irq2 pa12/irq3 pa13/fiq pa14/sck0 pa15/txd0 pa16/rxd0 pa17/sck1 pa18/txd1/ntri pa19/rxd1 pb11 pb12 pb13 pb14 pb15 pb16 tms tdo tdi tck ntrst usart2 2 pdc channels pa20/sck2 pa21/txd2 pa22/rxd2 spi: serial peripheral interface tc: timer counter block 1 tc3 tc4 tc5 pa0/tclk3 pa3/tclk4 pa6/tclk5 pa1/tioa3 pa2/tiob3 pa4/tioa4 pa5/tiob4 pa7/tioa5 pa8/tiob5 pb10 pb4/irq5 pb5 pb1 pb2 pb8 pb9 pb3/irq4 pa9/irq0 pa24/miso pa25/mosi pa26/npcs0/nss pa27/npcs1 pa23/spck pa28/npcs2 pa29/npcs3 pb18/bms ebi user interface 2 pdc channels pb0 pb17 clock generator pll mcko pllrc xin xout 16 mhz chip id nwait jtagsel gndbu jtagsel 4-channel adc0 ad0 ad1 ad2 ad3 4-channel adc1 ad4 ad5 ad6 ad7 advref pb6/ad0trig pb7/ad1trig piob controller pioa controller wd: watchdog timer nwdovf p i o a vddio, vddcore gnd jtag wakeup shdn dac0 dac1 davref da0 da1 vddpll xout32 32.768 khz vddbu nrstbu rtc: real time clock apmc: advanced power management controller gndpll vdda gnda xin32 battery backup analog
9 AT91M55800A 1745cs?atarm?05/02 architectural overview the AT91M55800A microcontroller integrates an arm7tdmi with its embedded ice interface, memories and peripherals. its architecture consists of two main buses, the advanced system bus (asb) and the advanced peripheral bus (apb). designed for maximum performance and controlled by the memory controller, the asb interfaces the arm7tdmi processor with the on-chip 32-bit memories, the external bus interface (ebi) and the amba ? bridge. the amba bridge drives the apb, which is designed for accesses to on-chip peripherals and optimized for low power consumption. the AT91M55800A microcontroller implements the ice port of the arm7tdmi proces- sor on dedicated pins, offering a complete, low cost and easy-to-use debug solution for target debugging. memory the AT91M55800A microcontroller embeds 8k bytes of internal sram. the internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. the AT91M55800A microcontroller features an external bus interface (ebi), which enables connection of external memories and application-specific peripherals. the ebi supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. the ebi implements the early read protocol, enabling faster memory accesses than standard memory interfaces. peripherals the AT91M55800A microcontroller integrates several peripherals, which are classified as system or user peripherals. all on-chip peripherals are 32-bit accessible by the amba bridge, and can be programmed with a minimum number of instructions. the peripheral register set is composed of control, mode, data, status and enable/dis- able/status registers. an on-chip, 8-channel peripheral data controller (pdc) transfers data between the on- chip usarts/spi and the on and off-chip memories without processor intervention. one pdc channel is connected to the receiving channel and one to the transmitting channel of each usart and of the spi. most importantly, the pdc removes the processor interrupt handling overhead and sig- nificantly reduces the number of clock cycles required for a data transfer. it can transfer up to 64k contiguous bytes. as a result, the performance of the microcontroller is increased and the power consumption reduced. system peripherals the external bus interface (ebi) controls the external memory and peripheral devices via an 8- or 16-bit data bus and is programmed through the apb. each chip select line has its own programming register. the advanced power management controller (apmc) optimizes power consumption of the product by controlling the clocking elements such as the oscillators and the pll, system and user peripheral clocks, and the power supplies. the advanced interrupt controller (aic) controls the internal interrupt sources from the internal peripherals and the eight external interrupt lines (including the fiq), to provide an interrupt and/or fast interrupt request to the arm7tdmi. it integrates an 8-level prior- ity controller and, using the auto-vectoring feature, reduces the interrupt latency time. the real-time clock (rtc) peripheral is designed for very low power consumption, and combines a complete time-of-day clock with alarm and a two-hundred year gregorian calendar, complemented by a programmable periodic interrupt. the parallel input/output controllers (pioa and piob) control the 58 i/o lines. they enable the user to select specific pins for on-chip peripheral input/output functions, and
10 AT91M55800A 1745cs?atarm?05/02 general-purpose input/output signal pins. the pio controllers can be programmed to detect an interrupt on a signal change from each line. the watchdog (wd) can be used to prevent system lock-up if the software becomes trapped in a deadlock. the special function (sf) module integrates the chip id and reset status registers. user peripherals three usarts, independently configurable, enable communication at a high baud rate in synchronous or asynchronous mode. the format includes start, stop and parity bits and up to 8 data bits. each usart also features a timeout and a time guard register, facilitating the use of the two dedicated peripheral data controller (pdc) channels. the six 16-bit timer/counters (tc) are highly programmable and support capture or waveform modes. each tc channel can be programmed to measure or generate differ- ent kinds of waves, and can detect and control two input/output signals. each tc also has three external clock signals. the spi provides communication with external devices in master or slave mode. it has four external chip selects which can be connected to up to 15 devices. the data length is programmable, from 8- to 16-bit. the two identical 4-channel 10-bit analog-to-digital converters (adc) are based on a successive approximation register (sar) approach. the two identical single-channel 10-bit digital-to-analog converters (dac).
11 AT91M55800A 1745cs?atarm?05/02 associated documentation table 4 . associated documentation product information document title AT91M55800A internal architecture of processor arm/thumb instruction sets embedded in-circuit-emulator arm7tdmi (thumb) datasheet external memory interface mapping peripheral operations peripheral user interfaces AT91M55800A datasheet dc characteristics power consumption thermal and reliability considerations ac characteristics AT91M55800A electrical characteristics product overview ordering information packaging information soldering profile AT91M55800A summary datasheet (this document)
12 AT91M55800A 1745cs?atarm?05/02 product overview power supplies the AT91M55800A has 5 kinds of power supply pins: vddcore pins, which power the chip core vddio pins, which power the i/o lines vddpllpins,whichpowertheoscillatorandpllcells vdda pins, which power the analog peripherals adc and dac vddbu pins, which power the rtc, the 32768 hz oscillator and the shut-down logic of the apmc vddio and vddcore are separated to permit the i/o lines to be powered with 5v, thus resulting in full ttl compliance. the following ground pins are provided: gnd for both vddcore and vddio gndpll for vddpll gndaforvdda gndbu for vddbu all of these ground pins must be connected to the same voltage (generally the board electric ground) with wires as short as possible. gndpll, gnda and gndbu are pro- vided separately in order to allow the user to add a decoupling capacitor directly between the power and ground pads. in the same way, the pll filter resistor and capac- itors must be connected to the device and to gndbu with wires as short as possible. also, the external load capacitances of the main oscillator crystal and the 32768 hz crystal must be connected respectively to gndpll and to gndbu with wires as short as possible. the main constraints applying to the different voltages of the device are: vddbu must be lower than or equal to vddcore vdda must be higher than or equal to vddcore vddcore must be lower than or equal to vddio the nominal power combinations supported by the AT91M55800A are described in the following table: input/output considerations after the reset, the peripheral i/os are initialized as inputs to provide the user with maxi- mum flexibility. it is recommended that in any application phase, the inputs to the AT91M55800A microcontroller be held at valid logic levels to minimize the power consumption. ta ble 5. nominal power combinations vddio vddcor e vdda vddpll vddbu maximum operating frequency 3v 3v 3v 3v 3v 33 mhz 3.3v 3.3v 3.3v 3.3v 3.3v 33 mhz 5v 3.3v 3.3v 3.3v 3.3v 33 mhz
13 AT91M55800A 1745cs?atarm?05/02 master clock master clock is generated in one of the following ways, depending on programming in the apmc registers: from the 32768 hz low-power oscillator that clocks the rtc the on-chip main oscillator, together with a pll, generate a software-programmable main clock in the 500 hz to 33 mhz range. the main oscillator can be bypassed to allow the user to enter an external clock signal. the master clock (mck) is also provided as an output of the device on the mcko pin, whose state is controlled by the apmc module. reset reset restores the default states of the user interface registers (defined in the user inter- face of each peripheral), and forces the arm7tdmi to perform the next instruction fetch from address zero. aside from the program counter, the arm7tdmi registers do not have defined reset states. nrst pin nrst is active low-level input. it is asserted asynchronously, but exit from reset is syn- chronized internally to the mck. at reset, the source of mck is the slow clock (32768 hz crystal), and the signal presented on mck must be active within the specification for a minimum of 10 clock cycles up to the rising edge of nrst, to ensure correct operation. watchdog reset the watchdog can be programmed to generate an internal reset. in this case, the reset has the same effect as the nrst pin assertion, but the bms and ntri pins are not sampled. boot mode and tri-state mode are not updated. if the nrst pin is asserted and the watchdog triggers the internal reset, the nrst pin has priority. emulation functions tri-state mode the AT91M55800A provides a tri-state mode, which is used for debug purposes. this enables the connection of an emulator probe to an application board without having to desolder the device from the target board. in tri-state mode, all the output pin drivers of the AT91M55800A microcontroller are disabled. to enter tri-state mode, the ntri pin must be held low during the last 10 clock cycles before the rising edge of nrst. for normal operation the ntri pin must be held high during reset, by a resistor of up to 400k ohm. ntri is multiplexed with i/o line pa18 and usart 1 serial data transmit line txd1. standard rs232 drivers generally contain internal 400k ohm pull-up resistors. if txd1 is connected to a device not including this pull-up, the user must make sure that a high level is tied on ntri while nrst is asserted. jtag/ice debug mode arm standard embedded in-circuit emulation is supported via the jtag/ice port. it is connected to a host computer via an external ice interface. the jtag/ice debug mode is enabled when jtagsel is low. in ice debug mode the arm core responds with a non-jtag chip id which identifies the core to the ice system. this is not jtag compliant.
14 AT91M55800A 1745cs?atarm?05/02 ieee 1149.1 jtag boundary- scan jtag boundary-scan is enabled when jtagsel is high. the functions sample, extest and bypass are implemented. there is no jtag chip id. the special func- tion module provides a chip id which is independent of jtag. it is not possible to switch directly between jtag and ice operations. a chip reset must be performed (nrst and ntrst) after jtagsel is changed. memory controller the arm7tdmi processor address space is 4g bytes. the memory controller decodes the internal 32-bit address bus and defines three address spaces: internal memories in the four lowest megabytes middle space reserved for the external devices (memory or peripherals) controlled by the ebi internal peripherals in the four highest megabytes in any of these address spaces, the arm7tdmi operates in little-endian mode only. internal memories the AT91M55800A microcontroller integrates an 8-kbyte primary sram bank. this memory bank is mapped at address 0x0 (after the remap command), allowing arm7tdmi exception vectors between 0x0 and 0x20 to be modified by the software. the rest of the bank can be used for stack allocation (to speed up context saving and restoring), or as data and program storage for critical algorithms. all internal memory is 32 bits wide and single-clock cycle accessible. byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one cycle. fetching thumb or arm instructions is supported and internal memory can store twice as many thumb instructions as arm ones. boot mode select the arm reset vector is at address 0x0. after the nrst line is released, the arm7tdmi executes the instruction stored at this address. this means that this address must be mapped in nonvolatile memory after the reset. the input level on the bms pin during the last 10 clock cycles before the rising edge of the nrst selects the type of boot memory (see table 5). the bms pin is multiplexed with the i/o line pb18 that can be programmed after reset like any standard pio line. remap command the arm vectors (reset, abort, data abort, prefetch abort, undefined instruction, interrupt, fast interrupt) are mapped from address 0x0 to address 0x20. in order to allow these vectors to be redefined dynamically by the software, the AT91M55800A microcontroller uses a remap command that enables switching between the boot mem- ory and the internal ram bank addresses. the remap command is accessible through the ebi user interface, by writing one in rcb of ebi_rcr (remap control register). performing a remap command is mandatory if access to the other external devices (con- nected to chip selects 1 to 7) is required. the remap operation can only be changed back by an internal reset or an nrst assertion. ta ble 6. boot mode select bms boot mode 1 external 8-bit memory on ncs0 0 external 16-bit memory on ncs0
15 AT91M55800A 1745cs?atarm?05/02 abort control the abort signal providing a data abort or a prefetch abort exception to the arm7tdmi is asserted when accessing an undefined address in the ebi address space. no abort is generated when reading the internal memory or by accessing the internal peripherals, whether the address is defined or not. external bus interface the external bus interface handles the accesses between addresses 0x0040 0000 and 0xffc0 0000. it generates the signals that control access to the external devices, and can configure up to eight 16-mbyte banks. in all cases it supports byte, half-word and word aligned accesses. for each of these banks, the user can program: number of wait states number of data float times (wait time after the access is finished to prevent any bus contention in case the device is too long in releasing the bus) data bus width (8-bit or 16-bit) with a 16-bit wide data bus, the user can program the ebi to control one 16-bit device (byte access select mode) or two 8-bit devices in parallel that emulate a 16- bit memory (byte-write access mode). the external bus interface features also the early read protocol, configurable for all the devices, that significantly reduces access time requirements on an external device.
16 AT91M55800A 1745cs?atarm?05/02 peripherals the AT91M55800A peripherals are connected to the 32-bit wide advanced peripheral bus. peripheral registers are only word accessible. byte and half-word accesses are not supported. if a byte or a half-word access is attempted, the memory controller automati- cally masks the lowest address bits and generates a word access. each peripheral has a 16-kbyte address space allocated (the aic only has a 4-kbyte address space). peripheral registers the following registers are common to all peripherals: control register ? write only register that triggers a command when a one is written to the corresponding position at the appropriate address. writing a zero has no effect. mode register ? read/write register that defines the configuration of the peripheral. usually has a value of 0x0 after a reset. data registers ? read and/or write register that enables the exchange of data between the processor and the peripheral. status register ? read only register that returns the status of the peripheral. enable/disable/status registers ? shadow command registers. writing a one in the enable register sets the corresponding bit in the status register. writing a one in the disable register resets the corresponding bit and the result can be read in the status register. writing a bit to zero has no effect. this register access method maximizes the efficiency of bit manipulation, and enables modification of a register with a single non-interruptible instruction, replacing the costly read-modify-write operation. unused bits in the peripheral registers are shown as ??? and must be written at 0 for upward compatibility. these bits read 0. peripheral interrupt control the interrupt control of each peripheral is controlled from the status register using the interrupt mask. the status register bits are anded to their corresponding interrupt mask bits and the result is then ored to generate the interrupt source signal to the advanced interrupt controller. the interrupt mask is read in the interrupt mask register and is modified with the inter- rupt enable register and the interrupt disable register. the enable/disable/status (or mask) makes it possible to enable or disable peripheral interrupt sources with a non- interruptible single instruction. this eliminates the need for interrupt masking at the aic or core level in real-time and multi-tasking systems. peripheral data controller an on-chip, 8-channel peripheral data controller (pdc) transfers data between the on- chip usarts/spi and the on and off-chip memories without processor intervention. one pdc channel is connected to the receiving channel and one to the transmitting channel of each usart and spi. the user interface of a pdc channel is integrated in the memory space of each periph- eral. it contains a 32-bit address pointer register and a 16-bit count register. when the programmed data is transferred, an end of transfer interrupt is generated by the corre- sponding peripheral. most importantly, the pdc removes the processor interrupt handling overhead and sig- nificantly reduces the number of clock cycles required for a data transfer. it can transfer up to 64k contiguous bytes. as a result, the performance of the microcontroller is increased and the power consumption reduced.
17 AT91M55800A 1745cs?atarm?05/02 system peripherals apmc: advanced power management controller the AT91M55800A advanced power management controller allows optimization of power consumption. the apmc enables/disables the clock inputs of most of the periph- erals and the arm core. moreover, the main oscillator, the pll and the analog peripherals can be put in standby mode allowing minimum power consumption to be obtained. the apmc provides the following operating modes: normal mode: clock generator provides clock to the entire chip except the rtc. wait mode: arm core clock deactivated slow clock mode: clock generator deactivated, master clock 32 khz standby mode: rtc active, all other clocks disabled power-down mode: rtc active, supply on the rest of the circuit deactivated rtc: real time clock the AT91M55800A features a real-time clock (rtc) peripheral that is designed for very low power consumption. it combines a complete time-of-day clock with alarm and a two-hundred year gregorian calendar, complemented by a programmable periodic interrupt. the time and calendar values are coded in binary-coded decimal (bcd) format. the time format can be 24-hour mode or 12-hour mode with an am/pm indicator. updating time and calendar fields and configuring the alarm fields is performed by a par- allel capture on the 32-bit data bus. an entry control is performed to avoid loading registers with incompatible bcd format data or with an incompatible date according to the current month/ year/century. aic: advanced interrupt controller the aic has an 8-level priority, individually maskable, vectored interrupt controller, and drives the nirq and nfiq pins of the arm7tdmi from: the external fast interrupt line (fiq) the six external interrupt request lines (irq0 - irq5) the interrupt signals from the on-chip peripherals the aic is largely programmable offering maximum flexibility, and its vectoring features reduce the real-time overhead in handling interrupts. the aic also features a spurious vector, which reduces spurious interrupt handling to a minimum, and a protect mode that facilitates the debug capabilities. pio: parallel i/o controller the AT91M55800A has 58 programmable i/o lines. 13 pins are dedicated as general- purpose i/o pins. the other i/o lines are multiplexed with an external signal of a periph- eral to optimize the use of available package pins. the pio lines are controlled by two separate and identical pio controllers called pioa and piob. the pio controller enables the generation of an interrupt on input change and insertion of a simple input glitch filter on any of the pio pins. wd: watchdog the watchdog is built around a 16-bit counter, and is used to prevent system lock-up if the software becomes trapped in a deadlock. it can generate an internal reset or inter- rupt, or assert an active level on the dedicated pin nwdovf. all programming registers are password-protected to prevent unintentional programming. sf: special function the AT91M55800A provides registers which implement the following special functions. chip identification reset status
18 AT91M55800A 1745cs?atarm?05/02 user peripherals usart: universal synchronous/ asynchronous receiver transmitter the AT91M55800A provides three identical, full-duplex, universal synchronous/asyn- chronous receiver/transmitters. each usart has its own baud rate generator, and two dedicated peripheral data con- troller channels. the data format includes a start bit, up to 8 data bits, an optional programmable parity bit and up to 2 stop bits. the usart also features a receiver timeout register, facilitating variable-length frame support when it is working with the pdc, and a time-guard register, used when interfac- ing with slow remote equipment. tc: timer/counter the AT91M55800A features two timer/counter blocks that include three identical 16-bit timer/counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval mea- surement, pulse generation, delay timing and pulse-width modulation. the timer/counters can be used in capture or waveform mode, and all three counter channels can be started simultaneously and chained together. spi: serial peripheral interface the spi provides communication with external devices in master or slave mode. it has four external chip selects that can be connected to up to 15 devices. the data length is programmable, from 8- to 16-bit. adc: analog-to-digital converter the two identical 4-channel 10-bit analog-to-digital converters (adc) are based on a successive approximation register (sar) approach. each adc has 4 analog input pins, ad0 to ad3 and ad4 to ad7, digital trigger input ad0trig and ad1trig pins, and provides an interrupt signal to the aic. both adcs share the analog power supply vdda and gnda pins, and the input reference voltage advref pin. each channel can be enabled or disabled independently, and has its own data register. the adc can be configured to automatically enter sleep mode after a conversion sequence, and can be triggered by the software, the timer/counter, or an external signal. dac: digital-to-analog converter two identical 1-channel 10-bit digital-to-analog converters (dac). each dac has an analog output pin, da0 and da1, and provides an interrupt signal to the aic da0irq and da1irq. both dacs share the analog power supply vdda and gnda pins, and the input reference davref.
19 AT91M55800A 1745cs?atarm?05/02 ordering information table 7 . ordering information ordering code package temperature operating range AT91M55800A-33ai tqfp 176 industrial (-40 cto85 c) AT91M55800A-33ci bga 176
20 AT91M55800A 1745cs?atarm?05/02 packaging information figure 4. 176-lead thin quad flat pack package drawing pin 1 aaa bbb cc 1 ddd 2 3 s l1 r1 r2 0.25 ccc 1
21 AT91M55800A 1745cs?atarm?05/02 table 8 . common dimensions (mm) symbol min nom max c 0.09 0.20 c1 0.09 0.16 l 0.45 0.6 0.75 l1 1.00 ref r2 0.08 0.2 r1 0.08 s0.2 q0 3.5 7 10 211 12 13 311 12 13 a 1.6 a1 0.05 0.15 a2 1.35 1.4 1.45 tolerances of form and position aaa 0.2 bbb 0.2 table 9 . lead count dimensions (mm) pin count d/e bsc d1/e1 bsc bb1 e bsc ccc ddd min nom max min nom max 176 26.024.00.170.200.270.170.200.230.500.100.08 table 1 0. device and 176-lead tqfp package maximum weight 2023 mg
22 AT91M55800A 1745cs?atarm?05/02 figure 5. 176-ball ball grid array package drawing table 1 1. device and 176-ball bga package maximum weight 606 mg notes: 1. package dimensions conform to jedec mo-205 2. dimensioning and tolerancing per asme y14.5m-1994 3. all dimensions in mm 4. solder ball position designation per jesd 95-1, spp-010 5. primary datum z and seating plane are defined by the spherical crowns of the solder balls symbol maximum aaa 0.1 bbb 0.1 ddd 0.1 eee 0.03 fff 0.04 ggg 0.03 hhh 0.1 kkk 0.1 top view bottom view
23 AT91M55800A 1745cs?atarm?05/02 soldering profile table 12 gives the recommended soldering profile from j-std-20. small packages may be subject to higher temperatures if they are reflowed in boards with larger components. in this case, small packages may have to withstand tempera- turesofupto235 c, not 220 c (ir reflow). recommended package reflow conditions depend on package thickness and volume. see table 13. notes: 1. the packages are qualified by atmel by using ir reflow conditions, not convection or vpr. 2. by default, the package level 1 is qualified at 220 c (unless 235 c is stipulated). 3. the body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability. a maximum of three reflow passes is allowed per component. table 12. soldering profile convection or ir/convection vpr average ramp-up rate (183 c to peak) 3 c/sec. max. 10 c/sec. preheat temperature 125 c25 c 120 sec. max temperature maintained above 183 c 60 sec. to 150 sec. time within 5 c of actual peak temperature 10 sec. to 20 sec. 60 sec. peak temperature range 220 +5/-0 cor 235 +5/-0 c 215 to 219 cor 235 +5/-0 c ramp-down rate 6 c/sec. 10 c/sec. time 25 c to peak temperature 6 min. max table 13. recommended package reflow conditions (tqfp and pbga) (1,2,3) parameter temperature convection 220 +5/-0 c vpr 215 to 219 c ir/convection 220 +5/-0 c
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